MPC860TZQ50D4

Product Summary

The MPC860TZQ50D4 is a versatile one-chip integrated microprocessor and peripheral combination designed for a variety of controller applications. It particularly excels in communications and networking systems. The MPC860TZQ50D4 implements the PowerPC architecture and contains a superset of Freescale’s Quad Integrated Communications Controller (QUICC.), referred to here as the QUICC, RISC Communications Proccessor Module (CPM). The CPM from the MPC860TZQ50D4 QUICC has been enhanced by the addition of the inter-integrated controller (I2C) channel.

Parametrics

MPC860TZQ50D4 absolute maximum ratings: (1)Supply voltage, VDDH: -0.3 to 4.0V; VDDL: -0.3 to 4.0V; KAPWR: -0.3 to 4.0V; VDDSYN: -0.3 to 4.0V; (2)Input voltage, Vin: GND -0.3 to VDDH V; (3)Temperature (standard), TA(min): 0℃;p Tj(max): 95℃; (4)Temperature 3 (extended), TA(min): -40℃; Tj(max): 95℃; (5)Storage temperature range, Tstg: -55 to 150℃.

Features

MPC860TZQ50D4 features: (1)Embedded single-issue, 32-bit PowerPCTM core (implementing the PowerPC architecture) with thirty-two 32-bit general-purpose registers (GPRs); (2)The core performs branch prediction with conditional prefetch without conditional execution; (3)4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache; (4)16-Kbyte instruction caches are four-way, set-associative with 256 sets; 4-Kbyte instruction caches are two-way, set-associative with 128 sets; (5)8-Kbyte data caches are two-way, set-associative with 256 sets; 4-Kbyte data caches are two-way, set-associative with 128 sets; (6)Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache blocks; (7)Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and are lockable on a cache block basis; (8)MMUs with 32-entry TLB, fully-associative instruction, and data TLBs; (9)MMUs support multiple page sizes of 4-, 16-, and 512-Kbytes, and 8-Mbytes; 16 virtual address spaces and 16 protection groups; (10)Advanced on-chip-emulation debug mode; (11)Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits); (12)32 address lines; (13)Operates at up to 80 MHz; (14)Memory controller (eight banks).

Diagrams