(China (Mainland))
Product Summary
The XCR3032XL-10VQG44C is a 3.3V, 32-macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of two function blocks provide 750 usable gates. Pin-to-pin propagation delays are as fast as 4.5 ns with a maximum system frequency of 213 MHz.
Parametrics
XCR3032XL-10VQG44C absolute maximum ratings: (1)Output High voltage, VOH: 2.4V; VCC = 2.7V to 3.0V, IOH = -8 mA, VOH: 2.0V; IOH = –500 μA, VOH: 90% VCC V; (2)Output Low voltage IOL = 8 mA, VOL: 0.4 V; (3)Input leakage current, VIN = GND or VCC to 5.5V, IIL: -10 to 10 μA; (4)I/O High-Z leakage current VIN = GND or VCC to 5.5V, IIH: -10 to 10 μA; (5)Standby current VCC = 3.6V, ICCSB: 100 μA; (6)Dynamic current(5,6) f = 1 MHz, ICC: 0.25 mA; f = 50 MHz, ICC: 7.5 mA; (7)Input pin capacitance, f = 1 MHz, CIN: 8 pF; (8)Clock input capacitance, f = 1 MHz, CCLK: 12 pF; (9)I/O pin capacitance, f = 1 MHz, CI/O: 10 pF.
Features
XCR3032XL-10VQG44C features: (1)Low power 3.3V 32 macrocell CPLD; (2)4.5 ns pin-to-pin logic delays; (3)System frequencies up to 213 MHz; (4)32 macrocells with 750 usable gates; (5)Available in small footprint packages; (6)Optimized for 3.3V systems; (7)In-system programming; (8)Input registers; (9)Predictable timing model; (10)Up to 23 available clocks per function block; (11)Excellent pin retention during design changes; (12)Full IEEE Standard 1149.1 boundary-scan (JTAG); (13)Four global clocks; (14)Eight product term control terms per function block; (15)Fast ISP programming times; (16)Port Enable pin for dual function of JTAG ISP pins; (17)2.7V to 3.6V supply voltage at industrial temperature range; (18)Programmable slew rate control per macrocell; (19)Security bit prevents unauthorized access; (20)Refer to the CoolRunner XPLA3 family data sheet (DS012) for architecture description.
Diagrams
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IC ISP CPLD 32 MCELL3.3V 44-VQFP |
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